Integrating Logic Synthesis, Technology Mapping, and Retiming

This paper presents a method that combines logic synthesis, technology mapping, and retiming into a single integrated flow. The proposed integrated method is applicable to both standard cell and FPGA designs. An efficient implementation uses sequential And- Inverter Graphs (AIGs). Experiments on a variety of industrial circuits from the IWLS 2005 benchmarks show an average reduction of the clock period of 25%, compared to the traditional mapping without retiming, and by 20%, compared to traditional mapping followed by retiming applied as a post-processing step.