A 550ps Access-Time Compilable Sram In 65nm Cmos Technology

A fixed-configuration custom SRAM macro with a highly-scalable architecture was used as the basis for an ASIC SRAM compiler. The 256Kb fixed-configuration uses dynamic circuitry [1] and other design techniques, and has been demonstrated in silicon to have an access time of 550ps. The compilable SRAM extends the column mux options, and can be compiled from 2Kb to 1.1Mb. Novel circuitry is used for efficient redundancy implementation in both the row and column dimensions.