Runtime allocation and scheduling policies across network on chip architectures

Multicore processor architectures currently exist and the number of cores onchip and the heterogeneity of those cores is increasing. As the number of cores increase, bus architectures for onchip communication will no longer scale leading to network on chip interconnects. As the heterogeneity of those cores increase, the need to manage a variety of processor types will be necessary. These processors will range from standard general purpose processors, to vector floating point processors, to pure FPGA logic regions. To manage such a processor architecture will require knowledge of the network on chip, the configuration of the processor cores, and runtime state of the entire architecture. Communication costs can be measured, analyzed, and used to gain better system performance at runtime. With several architectures to gather general purpose and application-specific execution profiles, this runtime scheduler can be demonstrated and its performance measured. Dynamic profiling of the application communication patterns and the network on chip state prove to be extremely useful in making scheduling decisions. Three example architectures and application domains are examined to provide evidence for the above assertions. A general purpose synthetic benchmarking platform, a cryptographic acceleration platform, and a software defined radio platform are presented to demonstrate the performance that can be gained by an intelligent scheduling system on these new architectures. From these three examples, a single scheduler and allocation policy engine is presented that works well across all these platforms. Various aspects of the architectures are abstracted up to the scheduler, allowing a single algorithm to span any network on chip architecture and any amount of heterogeneity on that architecture.