Improving CMOS speed at low supply voltages

ICCD（1994）

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摘要

A common approach to reduce CMOS power consumption is to reduce the supply voltage. However, circuit speeds degrade rapidly as the supply voltage drops. This paper uses theoretical analyses and experiments to explore the effectiveness of circuit and process modifications for improving speed at low VDD. In particular, we find that circuits operating in ohmic mode have less speed-VDD sensitivity and thus run faster at low supply voltages

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关键词

sensitivity,cmos integrated circuits,power consumption,circuit analysis computing,cmos speed,ohmic mode,improving cmos speed,low supply voltages,sensitivity analysis,degradation,process control,propagation delay,low voltage

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