An evaluation of deep-submicron CMOS design optimized for operation at 77 K

Using a careful and insightful analysis of the possible benefits of 77 K CMOS in submicron technology from a decade ago [1], the development of 77 K CMOS in present-day deep submicron technology is evaluated. It is found that the basic principles from the earlier study—that the real benefit of 77 K CMOS operation is the ability to provide “pure” scaling of the threshold voltage and thus to allow aggressive super-scaling of MOS transistor dimensions—not only holds in present-day CMOS processes, but is even more important in that regard. A detailed analysis of CMOS technology, digital circuit behavior, and analog circuit behavior is provided. It is noted that not only does properly-designed 77 K CMOS technology provide opportunities; it also addresses some of the most fundamental difficulties facing CMOS technology and CMOS circuit design.