Gate-oxide early-life failure identification using delay shifts
VTS（2010）
摘要
This paper presents experimental data from digital circuits on 90nm test chips, together with circuit simulations, to establish the following results: 1. The presence of a gate-oxide early-life failure (ELF) candidate transistor (also called infant mortality) in a logic gate results in delay shifts over time; 2. Delay shifts can be effective indicators of gate-oxide ELF suspects that may be detected using inexpensive digital techniques. These results can be utilized to overcome scaled-CMOS reliability challenges through effective ELF screening during production test or on-line during system operation for systems with built-in self-healing.
更多查看译文
关键词
built-in self-healing,circuit simulations,gate-oxide early-life failure identification,integrated circuit reliability,delay shifts over time,system operation,delay circuits,digital circuits,elf screening,scaled-cmos reliability,logic gate,built-in self test,failure analysis,cmos logic circuits,production test,size 90 nm,infant mortality,digital techniques,circuit simulation,logic testing,logic gates,system testing,ground penetrating radar,production systems,chip,stress,transistors
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要