A 0.1–0.3 V 40–123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters
J. Solid-State Circuits（2012）
摘要
This paper presents a 40-130 fJ/bit/ch on-chip data link design under a 0.1-0.3 V power supply. A bootstrapped CMOS repeater is proposed to drive a 10 mm on-chip bus. It features a -VDD to 2VDD swing to enhance the driving capability and reduces the sub-threshold leakage current. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. A test chip is fabricated in a 55 nm SPRVT Low-K CMOS process. The measured results demonstrate that for a 10 mm on-chip bus, the achievable data rate is 0.8-100 Mbps, and the energy consumption is 40-123 fJ per bit under 0.1-0.3 V VDD.
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关键词
leakage current reduction low-power,cmos integrated circuits,low-voltage,on-chip data link,energy efficient,data communication,radiofrequency interference,leakage currents,jitter,size 10 mm,bootstrapped circuit,sub-threshold circuit,system-on-chip,repeaters,precharge enhancement scheme,isi-suppressed bootstrapped cmos repeaters,size 55 nm,integrated circuit design,inter-symbol interference (isi),energy consumption,on-chip bus,test chip fabrication,leakage current reduction technique,interference suppression,isi jitter,data transmission,sprvt low-k cmos process,driving capability,subthreshold leakage current,intersymbol interference,bootstrap circuits,voltage 0.1 v to 0.3 v,low voltage,noise,logic gate,leakage current,logic gates,chip,system on chip,system on a chip,threshold voltage,boosting
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