Dynamic Instruction Cache Locking in Hard Real-Time Systems

Cache memories have been widely used in order to bridge the gap between high speed processors and relatively slower main memories, and thus to improve the overall performance of systems. How- ever in the context of hard real-time systems, they are a source of predictability problems. A lot of progress has been achieved to model caches to statically determine safe and precise bounds on the worst-case execution times (WCETs) estimates of tasks on architectures with caches. Nonetheless cache-aware WCET analysis techniques may not always be applicable or may be too pessimistic, because some memory accesses are unknown stati- cally. Another reason may come from a poorly doc- umented or non-deterministic cache line replace- ment policy. An alternative approach is to lock cache lines so as to make memory access times en- tirely predictable. In this paper, we consider an instruction cache and a task. We propose a an algorithm which par- titions the task into a set of regions. Each region owns statically a locked cache contents determined offline.