An Analysis of the Information Content of Address and Data Reference Streams.

Recent increases in VLSI processor speed and transistor density have not been matched by a proportionate increase in the number of I/O pins used to communicate information on and off chip. Since the number of I/O pins is limited by packaging technology and switching constraints, this trend is likely to continue, and I/O bandwidth will become the primary VLSI system performance bottleneck. This paper analyzes the potential of address and data stream coding in order to reduce bandwidth requirements