A vertical-junction field-effect transistor
IEEE Transactions on Electron Devices（1980）
摘要
A vertical JFET structure is described which allows realization of submicrometer channel-length devices using standard photolithographic techniques. The fabrication procedure utilizes an anisotropic etch followed by an impurity diffusion or implantation to define the channel. A numerical simulation of the JFET operation is implemented using a finite-element analysis technique. Typical devices exhi...
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关键词
anisotropic magnetoresistance,electric resistance,ion implantation,surface diffusion,finite element method,finite element analysis,impurities,bipolar transistor,finite element methods,numerical simulation,field effect transistor,etching,fabrication
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