A 100-Mhz Macropipelined VAX Microprocessor

A macropipelined CISC microprocessor was implemented in a 0.75-mum CMOS 3.3-V technology. The 1.3-million-transistor custom chip measures 1.62 x 1.46 cm2 and dissipates 16.3 W. The 100-MHz parts were benchmarked at 50 SPECmarks. This paper describes the on-chip clocking system as well as several high-performance logic and circuit techniques. Macroinstruction handling, micropipeline management, and control store structures highlight the design architecture. In addition, the hierarchical array organization and fast tag comparison technique of the primary cache are discussed. Power estimation procedures are outlined and the results are compared to measurements. Physical design and verification methods, and CAD tools are also described. After extensive functional verification efforts are described, chip and system test results conclude the paper.