Wafer-Level 3D Interconnects Via Cu Bonding

In this paper, we experimentally characterize structures obtained using 300 mm wafer-level Cu-Cu 3D integration. Bonding quality was assessed both from interfacial analysis including scanning acoustic microscopy and cross-section microscopy, and from electrical probing. Chains were formed between two wafers through bonded copper structures and electrically probed using through-silicon vias on the top wafer which had been thinned. We found that the electrical chain resistance measurements resulted in a very tight distribution and that the contribution due to the bonding interface resistance was negligible. A simple demonstration of transistor circuits operating in this structure was done where we compared performance of equivalent ring oscillators in the thin and thick silicon substrates, which showed similar performances. In conclusion, we have achieved a wafer-level Cu-Cu 3D integration approach capable of delivering yields and performance required for high volume manufacturing.