Physical Implementation of the Eight-Core Godson-3B Microprocessor

Journal of Computer Science and Technology(2011)

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摘要
The Godson-3B processor is a powerful processor designed for high performance servers including Dawning Servers. It offers significantly improved performance over previous Godson-3 series CPUs by incorporating eight CPU cores and vector computing units. It contains 582.6M transistors within 300mm2 area in 65 nm technology and is implemented in parallel with full hierarchical design flows. In Godson-3B, advanced clock distribution mechanisms including GALS (Globally Asynchronous Locally Synchronous) and clock mesh are adopted to obtain an OCV tolerable clock network. Custom-designed de-skew modules are also implemented to afford further latency balance after fabrication. The power reduction of Godson-3B is maintained by MLMM (Multi Level Multi Mode) clock gating and multi-threshold-voltage cells substitution schemes. The highest frequency of Godson-3B is 1.05GHz and the peak performance is 128GFlops (double-precision) or 256GFlops (single-precision) with 40W power consumption.
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关键词
physical implementation,hierarchical design flow,GALS,clock mesh,low power
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