A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU

Supporting both WCDMA with HSDPA and GSM/GPRS/EDGE, the 9.3 times 9.3 mm2 SoC fabricated in triple-Vth 65 nm CMOS, has three CPU cores and 20 separate power domains. Unused power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music playback scene dynamically stops a PLL and clock trees when not necessary and reduces power consumption ...