High Performance Vlsi Design Of Run_before For H.264/Avc Cavld

High-performance algorithm and VLSI architecture for H.264/AVC context-adaptive, variable-length decoder (CAVLD) run before computations are proposed to reduce the computation cycles. The run before values of input symbols are estimated if they are zeroes in parallel. By skipping the estimation step when long symbols starting with '000' are input, the architecture was drastically simplified while maintaining high performance. Experimental results showed that the performance for run before computations improved by 68% on average when four symbols were estimated in parallel in comparison with sequential estimation of the symbols. The area of run before is increased by 23% by the proposed architecture.