On general error cancellation based logic transformations: the theory and techniques

Rewiring is known to be a new class of logic restructuring technique at least equally powerful in flexibility compared to other logic transformation techniques while being wiring-sensitive, a property particularly useful for interconnect based circuit synthesis processes. One of the most mature rewiring techniques is the ATPG-based Redundancy Addition and Removal (RAR) technique which adds a redundant alternative wire to make an originally irredundant target wire become redundant and thus removable. However, all the currently known RAR techniques did not analyze and make use of unreachable states, which are abundant in sequential circuits. These unreachable states can be considered as input don't cares and can add an extra flexibility in locating alternative wires. In this dissertation, we study the fundamental theory and propose a reasoning scheme for locating alternative wires without performing wasteful redundancy tests. To explore the deeper effect of unreachable states, the concept is extended to illegal assignments and the fault independent redundancy identification is applied on illegal assignments to find flexibilities introduced by unreachable states. On the experiments carried for both MCNC and industry benchmarks, it is shown that using such an idea, a remarkable increase of more than 100% (averagely) in the number of alternative wires can be found, which should be quite useful as most of today's practical circuits are sequential. This thesis proposes a new Error Cancellation based Rewiring scheme (ECR) which can also do non-RAR based rewiring operations with high efficiency. Based on the notion of error cancellation, this thesis analyzes and reformulates the rewiring problem and develops a generalized rewiring scheme being able to detect more rewiring cases which are not obtainable by existing schemes while it still maintains low runtime complexity. Comparing with the most recent non-RAR rewiring tool IRRA, the total number of alternative wires found by our approach is about twice while CPU time is just slightly more(8%) upon benchmarks pre-optimized by rewriting of ABC. Besides the 1-1 rewiring scheme, this thesis also present the 1-m rewiring scheme, which is more general than the traditional 1-1 rewiring scheme. In the past, it has been experimentally suggested that only 30 to 40 % wires of optimized circuits are removable under rewiring scheme. In this dissertation, we show that based on an error cancellation based modeling, actually almost every circuit wire is removable theoretically. Besides, this modeling can also serve as a general (universal) rewiring framework containing the other rewiring techniques as its special cases. In addition to being practically desirable, being able to remove any wire can also be considered an atomic logic transformation step, since through repetitions of this process, virtually every circuit node can also be removable. For such an operation to be applicable, we propose a systematic flow graph error cancellation based rewiring (FECR) scheme being able to locate alternative logic candidates nearly for every target wire. Experimental results show that averagely 92.3% of all circuit wires are removable under this tool. As special 2-2 rewiring schemes, Generated Implication SuperGate (GISG) and extended symmetry detection are analyzed. Other logic transformation techniques such as rewriting, node merger, node addition and removal are also compared with error cancellation based rewiring scheme.