Design of a quasi-cyclic ldpc decoder using generic data packing scheme

This paper proposed a generic data packing scheme for quasi-cyclic LDPC codes decoder which has two advantages. Firstly, in this scheme no shift network is needed, it greatly reduces the area of the LDPC decoder. Secondly, in this scheme, all the messages in a row can be accessed from memories in one cycle, it increase the throughput of LDPC decoder. A LDPC decoder architecture using the data packing scheme is proposed. Based on this architecture, a multi rate decoder that supports all code rates and all code lengths in IEEE 802.16e standard is implemented using a SMIC 0.18μm CMOS technology. Compared to the existing LDPC decoder which uses the same parallel check node process unit, the proposed decoder has nearly the same throughput and achieves saving of 16% in area. Synthesis results also show that the area and throughput of the proposed decoder increases linearly with the number of process units.