A high performance pipelined discrete hilbert transform processor

A high performance pipelined discrete Hilbert transform (HT) processor is presented in this paper. The processor adopts fast Fourier transform (FFT) algorithm to compute discrete HT. FFT is an effectively method to compute the discrete HT, because the discrete HT can be calculated easily by multiplication with +j and -j in the frequency domain. The radix-2 FFT algorithm with decimation-in-frequency (DIF) and decimation-in-time (DIT) decomposition are both utilized to construct an efficiently discrete HT signal flow graph (SFG). Some stages in the discrete HT SFG don't include multiplications. These stages are combined into one stage by easy swapping operations to decrease the computational latency. The discrete HT processor is composed of four types pipelined processing elements (PE). Some constant multiplications in these PEs are optimized to reduce the hardware resource. Data being processed is of fixed point mode with 16-bit word width. The pipelined discrete HT processor has the ability to simultaneously perform calculations on the current frame of data, read input data for the next frame of data, and output the results of the previous frame of data. The symmetric property of twiddle factors is utilized to decrease half size of the read-only memory (ROM). Pipelined arithmetic units (adders and multipliers) are designed to enhance the performance of the discrete HT processor. The performance analysis with some previous paper approaches show that the proposed discrete HT processor has the shortest clock latency in discrete HT computation with same samples.