A 1V, 240 nW, 7 ppm/°C,high PSRR CMOS voltage reference circuit with curvature-compensation

Pengpeng Yuan,Dongmei Li,Xin Wang,Liyuan Liu,Chun Zhang,Zhihua Wang

ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings（2010）

引用 2|浏览26

暂无评分

摘要

A low power voltage reference is implemented in a standard 0.18μm CMOS process. The temperature coefficient (TC) of 7 ppm/°C is achieved in virtue of the output stage which consists of two transistors operating in subthreshold region and saturation region respectively. This kind of output stage is used to adjust the output voltage and compensate the curvature. The line sensitivity is 200 ppm/V in a supply voltage range of 1-3 V, and the power supply rejection ratio (PSSR) is -85 dB and -42 dB at 100Hz and 10 kHz, respectively. The maximum supply current is 240nA. The chip area is 0.016mm2. ©2010 IEEE.

查看译文

关键词

cmos integrated circuits,chip,transistors,power supply rejection ratio,photonic band gap,temperature measurement

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要