A DC-offset cancellation circuit for PGA in baseband communication

Guanzhong Huang,Yingjie Wu,Chaoli Zhong,Pingfen Lin

Circuits and Systems（2011）

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摘要

This paper introduces a novel DC-offset cancellation circuit for PGA in baseband communication. The output DC-offset is reduced from over one hundred millivolts to less than 4mV in all cases with power dissipation of 6.6μW. At the same time, spurious-free dynamic range (SFDR) of PGA output is 51.4dB and the settling time of 63dB gain step switching is 372μs. The chip is fabricated in 0.18μm CMOS technology.

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关键词

cmos integrated circuits,programmable-gain amplifier,telecommunication equipment,baseband communication,amplifiers,dc-offset cancellation circuit,power 6.6 muw,pga output,cmos technology,size 0.18 mum,spurious-free dynamic range,time 372 mus,output dc-offset

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