14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique

Phase-locked loops (PLLs) are a crucial building block in modern Systems-on-Chip (SoCs), which contain microprocessors, I/O interfaces, memories, power management, and communication systems. Fully synthesizable PLLs [1-2], designed using a pure digital design flow, have been proposed to reduce the design cost and allow easier integration. To achieve high-frequency resolution, PLLs are required to operate in fractional-N mode, in addition to integer-N mode. There are several architectures available [5-6] for realizing fractional-N operation. However, the existing topologies are not well suited for synthesis, as they require a time-to-digital converter (TDC) [3] and a digital-to-time converter (DTC) [4-5]. TDCs and DTCs are vulnerable to layout uncertainty, arising from automatic place and route (P&R), introducing linearity degradation and leading to poor in-band and out-of-band phase noise in PLLs. Injection locking is a promising technique for synthesizable PLLs. Unfortunately, it suffers from large spur caused by a periodic hard refresh, and limited fractional resolution, which is bounded to the inverse of the number of ring oscillator delay stages [6]. This paper describes a fully synthesizable fractional-N PLL with a soft injection-locking technique for smoothing switching and fine fractional resolution, and a cascading topology for suppressing the free-running oscillator phase noise over a wide loop bandwidth.