Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates

In this paper, we introduce -channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III–V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, of 6 A/ m ( V) and a room-temperature subthreshold swing (SS) of mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET performance by 1–2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.