A Fast Prototyping Framework for Analog Layout Migration with Planar Preservation

Analog layout generation in the advanced CMOS design is challenging by its increasing layout constraints and performance requirements. This situation becomes more intricate by the growing parasitic variability and manufacturing reliability. To facilitate the feasibility of template-based layout migration, this paper firstly introduces a layout preservation, which extracts placement and routing behaviors from an existing layout into a crossing graph via constrained Delaunay triangulation (CDT). And later this crossing graph can be migrated into multiple layouts with placement and routing reconnection. The proposed approach also provides a refinement for wire to optimize the performance metrics. This approach is applied to a variablegain amplifier (VGA), a folded-cascode operational amplifier (OpAmp) and a low dropout regulator (LDO). The experimental results demonstrate more possibility on layout migration, such that averagely more than 75% routing of migrated layout is generated by our approach. Additionally, it exhibits the productivity with qualified performance on different designs.