Static Differential NCL Gates: Towards Low Power

This brief proposes a new topology for implementing differential null convention logic gates. The new topology relies on the static implementation of conventional versions of such gates, and uses a set of extra minimum-sized transistors to cut off connections to the power rails in specific nodes, while the gate is switching. It shows that albeit the extra transistors add cost in area, they enable solid savings in dynamic and static power, and improve transition delays. Electrical simulation results for a Kogge-Stone adder case study led to savings of 67.3% in dynamic power and 61.9% in static power, 67.2% in energy per operation and 8.9% in forward propagation delay, when com-pared to a state-of-the-art differential topology