Bridging the Gap Between Hardware and Software Open Source Network Developments

The rise of network speeds to tens of gigabits per second poses a challenge to develop packet processing applications that can cope with such bit rates. Therefore, the need for a suitable open source system that can be used as a prototype platform to test new network functionality while ensuring line-rate processing, accurate timestamping, and reduced power consumption has become evident. All these requirements cannot be achieved by using software-only solutions, but rather with hardware-based platforms such as NetFPGA. The main obstacle when using this type of open source FPGA-based solution is the cost of development, in both time and hardware development skills required. The spread of new circuit synthesis tools using high-level languages opens the door for the development of hardware-based networking applications with reasonable development effort, compared to the use of traditional hardware description languages. In this article, we describe how existing open source hardware-based platforms for networking applications will be fueled by the change in the programming model of FPGAs provided by modern high-level synthesis tools. For this, we implemented a network flow monitor using high-level languages and compared the effort spent with respect to a traditional hardware development cycle. Preliminary results are very promising, given that development time is reduced from months to weeks.