A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS

Hui Pan,Yuan Yao,Mostafa Hammad,Junhua Tan,Karim Abdelhalim,Evelyn Wenting Wang,Rick C. J. Hsu,Derek Tam,Ichiro Fujimori

J. Solid-State Circuits（2014）

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摘要

This paper details a duplex architecture coupled with a linear Class-AB push-pull output stage that maximizes the power efficiency of linear wideband drivers for high-speed transceivers. The duplex driver merges transmission, reception, and termination; eliminates hybrid and termination overhead; and enables adaptive echo cancellation and rail-to-rail full-duplex operation. Implemented in 28 nm CMOS, this GPHY driver passes the 1000BASE-T and 100BASE-TX compliance tests using a 2.5 V supply and meets the transmit specifications for the half-duplex 10BASE-T Ethernet using a 3.3 V supply.

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关键词

cmos integrated circuits,cm compensation,linear class-ab push-pull output stage,100base-tx compliance tests,rail-to-rail,self-termination,driver circuits,size 28 nm,linear wideband drivers,duplex architecture,conformance testing,half-duplex 10base-t ethernet,gigabit ethernet,class-ab,adaptive echo cancellation,voltage 3.3 v,echo suppression,gphy driver,rail-to-rail class-ab output stage,driver,radio transceivers,full-duplex line driver,cmos integrated circuit,hybrid,high-speed transceivers,transceiver,push-pull,1000base-t compliance tests,voltage 2.5 v,duplex,local area networks

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