Better flash access via shape-shifting virtual memory pages.

ABSTRACTToday, many system designers try to fit the entire data set of an application in RAM to avoid the cost of accessing magnetic disk. However, for many data-centric applications this is not an option due to the capacity and high $/GB constraints of RAM. As a result, system designers are relying on NAND-Flash to augment RAM. However, rewriting applications to efficiently tier data between memory and storage is a complicated process and may take months or years. In this paper, we present Chameleon, a system to transparently augment RAM with NAND-Flash. Chameleon is the first transparent tiering system to provide low-latency accesses to both RAM and NAND-Flash. We show that applications using Chameleon outperform applications using state-of-the-art tiering mechanisms by providing more than two orders of magnitude improvement in latency for working sets that can fit in RAM. We also show that Chameleon provides up to 47% latency improvement for out-of-core applications. Finally, we show that Chameleon improves the flash device's lifetime by up to 8x.