Analog Circuit and Layout Synthesis Revisited.

In the first decade of the twenty first century, the first generation of analog synthesis tools - for circuit sizing and optimization and for physical design - moved from academic research projects, to startups, to integration on various standard platforms. In addition, we began to see some concerted efforts to formulate the verification problem in formal terms, albeit on rather simplified version of designs. In this invited talk I will try to summarize what we got right in that first generation effort, but also, what we got wrong. The "right" part is the idea that all design is optimization: continuous, combinatorial, geometric, etc. Formulating tough analog circuit and layout problems as the "right" optimization problem(s) got us the first generation of tools that did anything right. The "wrong" part was an incomplete appreciation of the importance of designer use models - how real people do real designs in this business. Closing that gap is one remaining challenge. Another is the leap to non-planar end-of-roadmap CMOS technologies, where lithographic and manufacturability concerns combine to create some difficult problems, and new opportunities for tool innovation. This talk will revisit and extend some elements of an earlier ISPD invited talk [1], and a recent talk at the 2011 CAV Frontiers in Analog Circuit(s) (FAC) workshop [2], and also introduce some new problems related to end-of-roadmap analog.