A DLL based low-phase-noise clock multiplier with offset-tolerant PFD
ASICON（2013）
摘要
This paper presents design techniques of a low-jitter delay-locked loop (DLL) based clock multiplier. The DLL is designed to generate 12 phases and a multiplied output in a continuous lock range from 40MHz to 110 MHz. A novel transecting PFD is introduced to prevent static phase offset. The core occupies an active area of 0.008 mm2 in a 65nm CMOS process and consumes 950uW from a supply voltage of 1.2V.
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关键词
cmos process,phase-frequency detector,dll based low-phase-noise clock multiplier,voltage 1.2 v,size 65 nm,frequency 40 mhz to 110 mhz,frequency multipliers,clocks,power 950 muw,integrated circuit design,transecting pfd,cmos digital integrated circuits,phase noise,low-jitter delay-locked loop,static phase offset,offset-tolerant pfd,delay lock loops
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