A Low Spur Cmos Phase-Locked Loop With Wide Tuning Range For Cmos Image Sensor

A CMOS phase-locked loop (PLL) with low reference spur and wide tuning range implemented in 0.18 mu m CMOS technology is presented in this paper. The design is based on the programmable integer-N PLL structure and the center frequency is around 480MHz for CMOS Image Sensor applications. A pseudo-differential current-starved multi-band ring oscillator is proposed to widen the tuning range. Several circuit techniques are used to minimize the phase frequency detector (PFD) UP/DN timing mismatch and charge pump (CP) current glitches, which reduce the reference spur. Implemented in the 0.18 m CMOS technology, the simulation results show that the -52.6dBc reference spur and the 94.4% tuning range (covering from 30MHz to 1050MHz) can be achieved.