A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization

ESSCIRC(2014)

引用 13|浏览12
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摘要
This paper presents a 65-nm CMOS, 1-V, 1.37-pJ/bit optical receiver with embedded equalizer, enabling adaptability to overcome channel losses and component variations. The digitally-controlled continuous-time linear equalizer (CTLE) consists of three cascaded tunable peaking stages offering 16-dB of adjustable low-frequency gain. Optical measurement results with a 30-Gb/s photodetector (PD) show that the receiver achieves 10-12 BER at 30 Gb/s for a 215-1 PRBS input with a -5.6-dBm input sensitivity. Using a lower bandwidth 14-Gb/s PD, the receiver can still reach 30 Gb/s at 10-12 BER with only a 0.6-dB degradation in input sensitivity. These measurement results demonstrate the effectiveness of the proposed receiver and the programmable cascaded CTLE.
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关键词
cmos integrated circuits,digitally-controlled continuous-time linear equalizer,cmos optical receiver,limiting amplifier,size 65 nm,digitally-tunable cascaded equalization,optical receiver,bit rate 30 gbit/s,channel loss,embedded equalizer,photodetectors,power 41 mw,voltage 1 v,optical receivers,transimpedance amplifier,cascaded continuous-time linear equalizer,programmable cascaded ctle,low-frequency gain,equalisers,optical measurement,component variations,photodetector
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