Uvm-Systemc-Ams Based Framework For The Correct By Construction Design Of Mems In Their Real Heterogeneous Application Context
2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS)(2014)
摘要
Each new embedded system tends to integrate more sensors with tight software-driven control, digitally assisted analog circuits, and heterogeneous structure. A more responsive simulation environment is needed to support the co-design and verification of such complex architectures including all its digital hardware/software and analog/multi-physical aspects using Multi-Disciplinary Virtual Prototyping ( MDVP). Taking a Micro-Electro-Mechanical System ( MEMS) vibration sensor as an example, we introduce a reusable framework based on the state-of-the-art technologies SystemC AMS, Finite Elements/Reduced-Order modeling, and UVM to design, simulate, and verify such systems in their real application context.
更多查看译文
关键词
Universal Verification Methodology (UVM), SystemC AMS, Micro-Electro-Mechanical System (MEMS), Multi-Disciplinary Virtual Prototyping (MDVP), design and verification methodology, dimensional analysis, bond graph formalism, reduced-order modeling
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要