A 3-mW 25-Gb/s CMOS transimpedance amplifier with fully integrated low-dropout regulator for 100GbE systems

Tampa, FL(2014)

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摘要
A novel inverter-based transimpedance amplifier (TIA) employing shunt-shunt inductive feedback and input series peaking is implemented in 65-nm CMOS for 100 Gbit Ethernet (100 GbE) receivers. The multiple peaking scheme provides an overall bandwidth enhancement ratio of 2.8 to deliver 42-dBQ of gain up to 24 GHz. To suppress the wideband noise from the TIA power supply and to alleviate the loading effect due to the supply bond-wires, a low-dropout regulator (LDO) with full-spectrum power supply rejection (PSR) of at least -12 dB is co-designed and integrated with the TIA. Measurements at 25 Gb/s show that the data eye RMS and peak-to-peak (P-P) jitters are improved by 15% and 24%, respectively, with the LDO enabled. The measured TIA sensitivity is -7.3 dBm at 25 Gb/s with a BER <; 10-12 for a 215-1 PRBS optical input. The TIA with LDO consumes 3 mW from a 1.2-V supply.
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cmos analogue integrated circuits,invertors,local area networks,operational amplifiers,cmos transimpedance amplifier,ethernet receivers,ldo,p-p jitters,tia power supply,tia sensitivity,bandwidth enhancement ratio,bit rate 25 gbit/s,data eye rms,full-spectrum power supply rejection,fully-integrated low-dropout regulator,input series peaking,inverter-based tia,inverter-based transimpedance amplifier,loading effect,low-dropout regulator,multiple-peaking scheme,optical input,peak-to-peak jitters,power 3 mw,shunt-shunt inductive feedback,size 65 nm,supply bond-wires,voltage 1.2 v,wideband noise suppression,100gbe receiver,cmos transimpedance amplifier (tia),bandwidth enhancement ratio (psr),low dropout regulator (ldo),power supply rejection,series inductive peaking,low dropout regulator,gain,noise,sensitivity,jitter,cmos integrated circuits,bandwidth
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