2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface

Point-to-point data transmission with clock-embedded signaling (CES) has been generally adopted in intra-panel interfaces, which need to support fine resolution, high frame rate, and large display size. Since CES embeds the clock-transition information in the data stream, it enables wide-range clock acquisition with PLL-based [1,2] or DLL-based [3-5] clock-and-data recovery (CDR) schemes. It also offers additional benefits of reduced EMI and low cost by eliminating the need for an additional clock channel or reference signal. For clock recovery, however, CES transmits a significant number of extra bits attached to each data packet to carry clock transition information. The number of extra bits is at least three [4] or four [3], sufficient to reduce the effect of inter-symbol interference (ISI) on clock transitions from adjacent random data patterns, providing cleaner reference to the clock recovery circuit. The repeated transitions in every data packet also intensify the spectral energy at the clock frequency as the data-rate increases, seriously aggravating EMI problem. This paper presents a DLL-based CDR with a new CES scheme that carries clock transitions with only one bit overhead but effectively sees the same ISI as a three- or four-bit overhead. By introducing a pattern-dependent clock embedding, our CES assimilates with random data transitions and almost eliminates the EMI issue. The CDR, implemented in 65nm CMOS, shows a lock range of 6.5 to 9Gb/s and a power efficiency of 0.63mW/Gb/s at 9Gb/s.