2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology

Mesut Meterelliyoz,Fuad H. Al-amoody,Umut Arslan,Fatih Hamzaoglu,Luke Hood,Manoj B. Lal,Jeffrey L. Miller, Anand Ramasundar, Dan Soltman, Ifar Wan,Yih Wang,Kevin Zhang

VLSIC（2014）

引用 1|浏览44

暂无评分

摘要

2nd generation 1Gbit 2GHz Embedded DRAM (eDRAM) with 4X lower self refresh power compared to prior generation is developed in 22nm Tri-Gate CMOS technology. Retention time has been improved by 3X (300us@95°C) by process and design optimizations. Source synchronous clocking is integrated in the design to reduce clock power without penalizing bandwidth. Charge pump power is reduced by 4X by employing comparator based regulation. Temperature controlled refresh enables minimum refresh power at all temperature conditions.

查看译文

关键词

cmos memory circuits,dram chips,uhf integrated circuits,charge pump circuits,clocks,comparators (circuits),integrated circuit design,optimisation,2nd generation embedded dram,charge pump power,comparator based regulation,edram,frequency 2 ghz,lower self refresh power,optimization,size 22 nm,source synchronous clocking,storage capacity 1 gbit,temperature controlled refresh,trigate cmos technology

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要