Session 15 overview: Digital PLLs: High-performance digital subcommittee
Solid-State Circuits Conference Digest of Technical Papers（2014）
摘要
The four papers presented in this session highlight developments in clock generation and distribution. These papers demonstrate the growing trend toward fully-synthesizable digital PLLs. Solutions presented relate to digital PLL integration, including power-supply noise rejection, temperature compensation, and fast frequency switching required in modern SoCs.
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