Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices

Electron Devices, IEEE Transactions  , Volume 61, Issue 6, 2014, Pages 2064-2070.

Cited by: 14|Bibtex|Views17|DOI:https://doi.org/10.1109/TED.2014.2318716
EI WOS
Other Links: academic.microsoft.com

Abstract:

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by ...More

Code:

Data:

Your rating :
0

 

Tags
Comments