Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by ...More