Data Acquisition System for the Belle II Experiment

The Belle II experiment, a new generation B-factory experiment at KEK to search for new physics beyond the standard model, is scheduled to start in 2017. The maximum trigger rate is expected to reach as high as 20 kHz with the raw event size of more than 1 MB and we set the designed trigger rate to 30 kHz for the data acquisition (DAQ) system. This requirement for the data acquisition is a big challenge. The Belle II DAQ system is a synchronous system based on a pipelined trigger flow control. Data from all subdetectors except for the Pixel Detector (PXD) digitized by the front-end are transferred to unified readout modules (COPPER) via a high speed optical link (Belle2link). The data are then collected by the readout PCs via Ethernet and the event building is performed in multiple steps. The built events are fed into High Level Trigger (HLT) to perform a software trigger. For processing data of the PXD, an FPGA-based readout system (ONSEN) is used. ONSEN performs a data reduction by exploiting expected hit positions of charged tracks reconstructed by the HLT. In order to test the full functionality of our DAQ design, we developed a down-scaled version of the Belle II DAQ system. The system was used in the combined beam test of Silicon Vertex Detector (SVD) and PXD in the DESY test beam performed in January of 2014. A slow control and real time data monitoring system were also implemented in this test. All components of this complex readout chain successfully cooperated to collect the beam data.