A pulsed resonance clocking for energy recovery
Circuits and Systems（2014）
摘要
An energy efficient and area saving local clocking scheme using new resonant techniques is illustrated with a bank of 1024 flip-flops. Energy recovering pulsed resonant (PR) clocking is designed to drive explicit-pulsed negative setup time latches. A pre-driver that generates tracking pulses at each transition of clock for dual edge (DET) operation is robust across PVT. While both the pre-driver and driver use inductors for energy reduction and recycling, the inductor area is small enough to fit over the active circuitry resulting in 40% power and active area reductions. The pulsed resonance (PR) operation needs only 1/10th the inductance of conventional LC resonant circuits. Monte Carlo simulations using 45nm device and interconnect models show that the design supports Dynamic Voltage and Frequency Scaling from 2GHz@1.3V to 200MHz@0.5V.
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关键词
LC circuits,Monte Carlo methods,flip-flops,logic design,DET operation,LC resonant circuits,Monte Carlo simulations,PR clocking,active area reductions,active circuitry,area saving local clocking scheme,dual edge operation,dynamic voltage and frequency scaling,energy efficient local clocking scheme,energy recovering pulsed resonant clocking,energy recycling,energy reduction,explicit-pulsed negative setup time latches,flip-flops,frequency 2 GHz,frequency 200 MHz,inductors,interconnect models,pre-driver,pulsed resonance clocking technique,size 45 nm,voltage 0.5 V,voltage 1.3 V,Clock Distribution Network (CDN),Dual Edge Triggering (DET),Dynamic Voltage Frequency Scaling (DVFS),Low Power,Resonant Clocking,System on Chip (SoC)
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