Successful void free gap fill of 3µm, high AR via middle, Through Silicon Vias at wafer level

Sara Thangaraju,Luke England,Mohamed A Rabie,Dejing Zhang,Gopal Kumarapuram, R W Mcgowan, A Selsley, Rudraskandan Ratnadurai Giridharan, Sijia Gu, V Seshachalam,Chingyue Wang,Shinichiro Kakita, S Baral, Wonhee Kim,H Edmundson

Advanced Semiconductor Manufacturing Conference（2014）

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摘要

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, Through Silicon Vias (TSV), of 3μm top entrant critical dimension (CD) and 50μm depth. Higher AR TSV integration is explored due to the lower stress influence of TSVs observed in adjacent CMOS devices.

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关键词

cmos integrated circuits,three-dimensional integrated circuits,vias,cmos device,high aspect ratio via middle,size 3 mum,size 50 mum,through silicon vias,top entrant critical dimension,void free gap fill,3d,koz,tsv,delamination,stress,resists,silicon

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