A comprehensive platform for thermal studies in TSV-based 3D integrated circuits

Papa Momar Souare,P Coudrain,J P Colonna,Vincent Fiori,A Farcy,F De Crecy,Andras Borbely, H Benjamaa,C Laviron,Sebastien Galloisgarreignot,Bastien Giraud,N Hotellier,R Franiatte, Stephane Dumas, C Chancel,Jeanmichel Riviere,J Pruvost,S Cheramy,C Tavernier,J Michailos,L Le Pailleur

Electron Devices Meeting（2014）

引用 7|浏览54

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摘要

We present an advanced and comprehensive platform for thermal dissipation studies in TSV-based 3D ICs. A 2-tier 3D test chip with through silicon via (TSV) and μ-bump is used for thermal characterization with unprecedented precision and design exploration capabilities. A comprehensive calibrated 3D finite element model is associated to provide a predictive tool that is able to simulate the thermal mapping in any given 3D interconnect configuration with minimal error. Guidelines are finally provided for thermal optimization of 3D designs with a precision far beyond the prior art.

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关键词

finite element analysis,integrated circuit interconnections,integrated circuit testing,thermal analysis,three-dimensional integrated circuits,μ-bump,2-tier 3d test chip,3d finite element model,3d interconnect configuration,tsv-based 3d integrated circuit,thermal characterization,thermal dissipation study,thermal mapping,through silicon via,3d ics,fem simalution,tsv,thermal,self heating,sensor,thermoelectric measurement

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