High performance 0.25 mu m p-MOSFETs with silicon-germanium channels for 300 K and 77 K operation
Washington, DC, USA（1991）
摘要
Quarter-micron Si/sub 1-x/Ge/sub x/ p-MOS devices with either thermal or PECVD oxides have been fabricated using an integrable process module (LOCOS isolation, threshold and deep well implants, p/sup +/ polysilicon gates, and TiSi/sub 2/) compatible with conventional 0.25 mu m CMOS with the Si/sub 1-x/Ge/sub x/ channel and Si cap deposited by selective UHV-CVD. Improvements in mobility and transconductance over deep submicron (0.25 mu m channel length) state-of-the-art Si p-MOSFETs were demonstrated by using silicon-germanium channels with low (10-25%) germanium content, both at room temperature (300 K) and low temperature (82 K). The use of Si/sub 1-x/Ge/sub x/ channels can provide better device performance in the same technology generation (same lithography, junction depth, etc.) and also help compensate for the external parasitic resistance penalty.<>
更多查看译文
关键词
cmos integrated circuits,ge-si alloys,carrier mobility,insulated gate field effect transistors,integrated circuit technology,semiconductor materials,0.25 micron,300 k,77 k,82 k,cmos compatible,locos,pecvd oxides,pmos device,si cap,si/sub 1-x/ge/sub x/ channel,sige-si,tisi/sub 2/,deep well implants,integrable process module,mobility,p-mosfets,p/sup +/ polysilicon gates,quarter micron devices,selective uhv-cvd,thermal oxides,transconductance,room temperature
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要