A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique

Yibin Ye,Muhammad M Khellah,Dinesh Somasekhar,A Farhang,Vivek De

Honolulu, HI, USA（2002）

引用 9|浏览18

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摘要

BLR is incorporated into a L1 cache design in a 100 nm dual-V/sub T/ technology to eliminate impacts of bitline leakage on performance and noise margin with minimal area overhead. Bitline delay is 23% better than the best conventional design, thus enabling 6 GHz operation at with 15% higher energy.

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关键词

cache storage,100 nm,16 kbyte,6 ghz,l1 cache,area overhead,bitline delay,bitline leakage reduction technique,dual threshold voltage technology,noise margin,voltage,energy storage,stability,frequency

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