A dual channel /spl Sigma//spl Delta/ ADC with 40MHz aggregate signal bandwidth

A Tabatabaei,Keith Onodera,Masoud Zargari,Hirad Samavati,David K Su

San Francisco, CA, USA（2003）

引用 21|浏览3

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摘要

A dual-channel /spl Sigma//spl Delta/ ADC has been integrated in 0.13/spl mu/m CMOS technology with an oversampling ratio of 4. The ADC employs a cascade of low-pass and band-pass modulators and achieves an aggregate quadrature signal bandwidth of 40MHz at a sampling frequency of 160MS/s and 54dB dynamic range while dissipating 175mW from a 2.5V supply.

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关键词

cmos integrated circuits,sigma-delta modulation,0.13 micron,175 mw,2.5 v,40 mhz,cmos technology,band-pass modulator,dual-channel sigma-delta adc,dynamic range,low-pass modulator,oversampling ratio,quadrature signal bandwidth

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