Comparison Of A Bsim3v3 And Ekv Most Model For A 0.5 Mu M Cmos Process And Implications For Analog Circuit Design

A BSIM3V3 and EKV model for a standard 0.5um CMOS process has been evaluated for analog applications. Critical small-signal parameters including output conductance and transconductance efficiency were simulated for devices with gate lengths ranging from 0.5um to 33um. In addition, the small-signal parameters were measured on test devices with similar dimensions. The results highlight the difficulty of obtaining a model that accurately predicts the operation of low voltage analog circuits.