A calibration-free 3V 16b 500kS/s 6mW 0.5mm2 ADC with 0.13 μm CMOS

Hee-Cheol Choi,Seung-Bin You,Ho-Young Lee,Ho-Jin Park

ieee（2004）

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摘要

A calibration-free 3V 6mW 16-bit 500kS/s cyclic ADC with an active die area of 0.5mm2 is implemented in a 0.13 μm CMOS. The proposed converter adopts a 2.5-bit/stage cyclic architecture and capacitor layout scheme to achieve improved matching accuracy, the DNL and INL of ±0.90 LSB and ±6.1 LSB, respectively.

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关键词

CMOS integrated circuits,analogue-digital conversion,0.13 μm CMOS,0.13 micron,3 V,6 mW,active die area,bit/stage cyclic architecture,calibration-free ADC,capacitor layout scheme,converter,improved matching accuracy,

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