A high-performance sub-0.25 /spl mu/m CMOS technology with multiple thresholds and copper interconnects

Su, L.,Schulz, R.,Adkisson, J.,Beyer, K.

Honolulu, HI, USA（1998）

引用 6|浏览0

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摘要

A sub-0.25 /spl mu/m technology in manufacturing that is targeted for high-performance CMOS applications is discussed. Aggressive groundrule scaling including SRAM cell size down to 5.4 /spl mu/m/sup 2/ is combined with multiple threshold voltage devices and the first technology in the industry to offer copper interconnects. These features result in minimum unloaded inverter delay of 12.7 ps and enable microprocessor frequencies above 480 MHz.

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关键词

CMOS integrated circuits,SRAM chips,copper,integrated circuit interconnections,logic gates,microprocessor chips,0.25 micron,12.7 ps,480 MHz,CMOS technology,SRAM,copper interconnect,groundrule scaling,inverter,microprocessor,multiple threshold voltage device,

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