Sub-60 nm physical gate length SOI CMOS

Isabel Y Yang, Kuanchou Chen,P Smeys,Jeffrey W Sleight, Li Lin,Mookseng Leong,Edward J Nowak, S Fung, E Maciejewski,P Varekamp, W Chu,H Park,P Agnello,S W Crowder,Fariborz Assaderaghi,Li Su

Washington, DC, USA（1999）

引用 13|浏览58

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摘要

This work addresses the design and optimization of high performance CMOS devices in the sub-60 nm regime. Aggressive scaling of the poly gate length is achieved by controlling the short-channel effects in partially-depleted SOI (Silicon-On-Insulator) CMOS devices. In addition, SOI specific design issues are examined to reduce device parasitics such as junction capacitance and history effect through the optimization of silicon film thickness. A high performance SOI CMOS with well-behaved 52 nm gate length devices is demonstrated.

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关键词

mosfet,silicon-on-insulator,60 nm,nfet device,pfet device,device parasitics,history effect,junction capacitance,partially-depleted soi cmos transistor,poly gate length scaling,short-channel effect,silicon film thickness optimization,short channel effect,silicon on insulator

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