A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

Peter Smeys,Vincent Mcgahay,I Yang,James W Adkisson, Kevin Beyer,Orest Bula, Zhi Chen,Baojin Chu, J W Culp,Sajal K Das,Anke K Eckert, L Hadel, M Hargrove, James G Herman, Li Lin,R Mann, E Maciejewski,Shreesh Narasimha, P Oneil,Stewart E Rauch, David Ryan, J Toomey, L Tsou, P Varekamp, R A Wachnik, Thomas Wagner,S Wu, Chonggun Yu, P Agnello, J F Connolly, S W Crowder,C Davis,Richard A Ferguson, Akihisa Sekiguchi,Li Su,Ronald D Goldblatt,T C Chen

Annual Symposium on VLSI（2000）

引用 36|浏览10

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摘要

This paper describes a 1.2V high performance 0.13 /spl mu/m generation SOI technology. Aggressive ground-rules and a tungsten damascene local interconnect render the densest 6T SRAM reported to date with a cell area of 2.16 /spl mu/m/sup 2/. This is accomplished with 248nm lithography, using optical proximity correction and resolution enhancement techniques on all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced low-k interlevel dielectric.

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关键词

cmos memory circuits,sram chips,copper,dielectric thin films,integrated circuit interconnections,proximity effect (lithography),silicon-on-insulator,ultraviolet lithography,0.13 mum,1.2 v,248 nm,6t sram,cu,cu interconnects,cu wiring,si-sio/sub 2/,advanced low-k interlevel dielectric,cell area,ground-rules,high performance soi cmos technology,interconnect performance,lithography,low-k beol dielectric,optical proximity correction,resolution enhancement techniques,tungsten damascene local interconnect,tungsten,silicon on insulator,dielectrics,threshold voltage,cmos technology

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