A 64B CPU Pair: Dual- and Single-Processor Chips

E. B. Cohen,N. J. Rohrer,P. Sandon,M. Canada,Cédric Lichtenau,M. Ringler,Paul Kartschoke,R. Floyd,J. Heaslip,M. Ross, Thomas Pflueger,R. Hilgendorf,P. McCormick,G. Salem,J. Connor,Stephen F. Geissler,D. Thygesen

IEEE International Solid-State Circuits Conference（2006）

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摘要

Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology. The dual-processor chip has split clock domains and power planes, 1 MB L2 cache per core and a shared processor interconnect bus. The single-processor chip shares the dual's basic core and cache design

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关键词

cache storage,integrated circuit interconnections,microprocessor chips,silicon-on-insulator,1 MByte,90 nm,L2 cache,Powertrade-architecture,clock domains,dual strained-silicon SOI technology,dual-processor chip,microprocessor chips,power planes,shared processor interconnect bus,single-processor chip

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